The Virtual Televisor is a combination of hardware and software that permits display of NBTVA-standard 32-line images on a Pentium-class PC. This will primarily be a description of the hardware phase of the project (a PC parallel-port interface), along with a few notes with respect to software issues. PC display of NBTV images has a number of advantages compared to mechanical or direct-display CRT systems, particularly with respect to the ability to display relatively large and flicker-free images. The computer-based display is thus well-suited for demonstrations to large groups, prolonged viewing of NBTV programming, and a reference display for the workbench when working on more conventional cameras or televisors.

Crystal Clock.

All sampling and timing operations of the Virtual Televisor software are referenced to a crystal-controlled frequency standard. U1 is configured using two stages (U1C and D) as a 3.2768 MHz TTL oscillator, with the remaining two gates (U1A and B) functioning to buffer the oscillator output. The 3.2768 MHz output of U1 (pin 6) is routed to an 8-stage binary counter (U2) wired to provide a divide-by-32 function. The result is a 51.2 KHz square wave at pin 10 of U2. Given the 32-line club-standard line rate of 400 Hz (32 x 12.5), the clock cycles 128 times (51,200/400) in the course of a single NBTV line. Given nominal timing values, approximately 120 of these clock cycles represent active video and 8 cycles represent sync.

Video Circuit

The video circuits are modified from Klaas Robers amplifier and DC-restoration/clamp circuits presented on the NBTVA website. The required three stages are built around a fast MAX494 (U3) quad-op-amp designed to operate from a single-ended 5V supply. Club-standard NBTV video is applied to J1 with a 10K GAIN control as a load. The variable output from the GAIN pot is AC-coupled to a non-inverting amplifier (U3D).  The output of U3D (pin 14) at a nominal 1.4V peak is coupled through a 1.82 mF capacitor (non-polarized) with a 330K resistive load. The time constant of this simple R-C network was selected to optimize the response of the simple diode clamp circuit implemented using U3A. The clamp level is adjustable via the CLAMP pot and the level can be monitored at TP5. The clamped video signal is then DC-coupled to a non-inverting amplifier (U3B) that provides both gain and DC offset. A simple two-diode network assures that negative or excessive positive voltage swings at the output of U3B cannot damage the input of the A/D converter (U4).

A/D Converter

U4 is a moderately-fast (1 microsecond conversion time) 8-bit flash analog to digital (A/D) converter. Assuming that the GAIN control has been set to provide 1.4V peak at the output of U3D and the CLAMP potentiometer has been set for a clamp level of 1.7 V, the DC-coupled output from U3B will have a peak white voltage of approximately 2.7V (essentially the voltage at the junction of the 10K and 12K resistors at the inverting input of U3B), a black-level voltage of ~0.58V, and a sync-level of 0V. If the WHITE potentiometer, which sets the positive voltage reference for the A/D conversion, is set for 2.7V (as measured at TP7), the output of U4 will be a count of 255 for white, ~55 for black, and 0 for white. Both the RD and WR inputs to U4 (active LOW) are connected to the 51.2 KHz clock line. Thus, 128 times during each line, when the clock line goes LOW, the output of the previous A/D conversion is available at the 8 output lines (D0-D7) and a new conversion is automatically started. Given the speed of U4 conversion cycle, the new A/D value will be available the next time the clock line goes LOW. In essence, this "pipeline" conversion scheme makes the operation of U4 completely automatic, with no software overhead to initiate conversions.

Output Multiplexer

A standard parallel port has only five input lines, four of which are used in this application. U5 functions as a four-pole double-throw digital switch, permitting the nominal 8-bit output of U4 to be read in two passes. The control pin (1) of U5 is controlled by bit D0 of the parallel port output. When the control pin is set LOW, the "high nibble" (bits D4-D7) of the A/D are read at the output of U5. When the control pin is set HIGH, the four output lines from U5 represent bits D1-D3 of the A/D converter and the clock bit. The software holds the control line HIGH and reads the output of U5 via the parallel port. When the clock bit goes LOW (signifying valid data), the software reads the modified LOW nibble (D1-D3) of the video data, the control pin of U5 is then set LOW, and the HIGH nibble (D4-D7) is read. The computer then formats the result as a 7-bit video value (ignoring the clock bit). The DOS-based Virtual Televisor software uses screen mode #13H, which provides a 320 x 200 display with 64 grayscale values (6-bits). The software displays the NBTV image in a 120 (H) by 96 (W) display, using a table to convert the 7-bit video values to 6-bits for display. The result is an image that is quite large by comparison with most mechanical systems (roughly equivalent to a mirror screw display, but sharper and free of the 12.5 Hz flicker that is characteristic of a mechanical televisor).

Audio and Power Subsystems

Because the NBTVA CDs all include audio tracks, a simple low-voltage IC power amplifier (U6) has been included. The right-channel CD signal (audio) is routed into J2 and across an audio VOLUME control. The output of U6 can drive an external speaker (8 ohms nominal) or low-impedance headphones at J3 (SPEAKER) or an internal speaker can be included inside the modest enclosure required to house the circuit. Power is supplied from a +9-12V wall-transformer type supply with the supply voltage applied to J4, a coaxial power connector. The DC supply voltage is routed through a POWER toggle or push-button switch and on to a low-power 5V regulator (U7) which provides the power for all the active circuits. The 5V bus also powers a front-panel LED POWER indicator. Because there are no high tension circuits, construction, testing, and adjustment of the interface presents a minimal hazard. Although fusing is not employed in the prototype, a 200 mA fuse could be included in the 9-12V line is desired.